Research Associate “Layout Engineer” (m/f/d)

The Barkhausen Institut performs research on the latest hardware, software and communication technologies and demonstrates their application in tomorrow's society. Our goal is to build a flexible and trustworthy IoT platform based on reliable electronics and secure communication methods.

At the earliest possible date we are looking for a

Research Associate “Layout Engineer” (m/f/d)

The position will initially be filled for a period of 2 years and will be remunerated in line with TV-L E-13. The position aims at supporting further academic qualification (e.g. PhD).

Your responsibilities will include

• Layout design and floorplanning of digital IC designs including memory macros and custom logic implementations
• Full layout and physical verification (DRC, LVS, ERC)
• Timing analysis and power optimization
• Support RTL-to-GDSII design flows for:
  • advanced process nodes, e.g. 12nm FDSOI
  • open-source PDKs, e.g. IHP 130nm
• Custom layout for analog blocks (training will be provided)

We expect the following

• MSc/Diploma or PhD degree in areas related to our research focus (Electrical/Computer Engineering) from renowned universities
• Good communication and writing skills in English
• An integrative and cooperative personality with excellent communication and social skills
• Prior experience with EDA tools for IC design, e.g. from Cadence or Synopsys

You are interested, but you don’t think you meet all the requirements of the job posting? Then you should know: We don’t hire resumes, we hire people. We are looking for potential and want to actively foster it. That’s why we encourage you to apply!

What we provide

• Training and exposure to chip tape-outs in advanced process nodes
• Experience in full development cycles of custom IC
• An open and creative team
• Agile working hours and workflows
• Cross-disciplinary projects